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TM
82C284
Clock Generator and Ready Interface for 80C286 Processors
Description
The Intersil 82C284 is a clock generator/driver which provides clock signals for 80C286 processors and support components. It also contains logic to supply READY to the CPU from either asynchronous or synchronous sources and synchronous RESET from an asynchronous input with hysteresis.
March 1997
Features
* Generates System Clock for 80C286 Processors * Generates System Reset Output from Schmitt Trigger Input - Improved Hysteresis * Uses Crystal or External Signal for Frequency Source * Dynamically Switchable between Two Input Frequencies * Provides Local READY and MULTIBUS READY Synchronization * Static CMOS Technology * Single +5V Power Supply * Available in 18 Lead CerDIP Package
Ordering Information
PART NUMBER CD82C284-12 ID82C284-10 ID82C284-12 TEMP. RANGE 0oC to +70oC -40oC to +85oC -40oC to +85oC PACKAGE PKG. NO.
18 Ld CERDIP F18.3 18 Ld CERDIP F18.3 18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP) TOP VIEW
Functional Diagram
RESET ARDY 1 18 VCC 17 ARDYEN 16 S1 15 S0 14 NC 13 PCLK 12 RESET 11 RES 10 CLK EFI F/C ARDYEN ARDY X1 X2 XTAL OSC MUX F/C X1 X2 GND 6 7 8 9 RES SYNCHRONIZER
RESET
SRDY 2 SRDYEN 3
READY 4 EFI 5
CLK
SYNCHRONIZER
SRDYEN SRDY
READY LOGIC
READY
S1 S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
FN2966.1
MULTIBUS
is a patented Intel bus.
82C284 Pin Description The following pin function descriptions are for the 82C284 clock generator.
PIN SYMBOL CLK NUMBER 10 TYPE O DESCRIPTION SYSTEM CLOCK: the signal used by the processor and support devices which must be synchronous with the processor. The frequency of the CLK output has twice the desired internal processor clock frequency. CLK can drive both TTL and CMOS level inputs. FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C, the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the processor CLK frequency while running for low-power operation, etc. CRYSTAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the internal oscillator. When F/C is LOW, the internal oscillator will drive the CLK output at the crystal frequency. The crystal frequency must be twice the desired internal processor clock frequency. EXTERNAL FREQUENCY IN: drives CLK when the F/C input is HIGH. The EFI input frequency must be twice the desired internal processor clock frequency. PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequency of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after the processor has been reset. ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARDY input. ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. ASYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The ARDY input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous outputs. SYNCHRONOUS READY ENABLE: an active LOW input which qualifies SRDY. SRDYEN selects SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold time must be satisfied for proper operation. SYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRDY input is qualified by the SRDYEN input. Setup and hold time must be satisfied for proper operation. READY: an active LOW output which signals to the processor that the current bus cycle is to be completed. The SRDY SRDYEN, ARDY, ARDYEN, S1, S0, and RES inputs control READY as explained later in the READY generator section. READY is an open drain output requiring an external pull-up resistor. STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 and S1 synchronize PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for proper operation RESET: an active HIGH output which is derived from the RES input RESET is used to force the system into an initial state. When RESET is active, READY will be active (LOW). RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES may be applied asynchronously to CLK. A Schmitt trigger input is provided on RES, so that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed response to synchronous inputs. SYSTEM POWER: The +5V Power Supply Pin. A 0.1F capacitor between VCC and GND is recommended for decoupling. SYSTEM GROUND: 0V
F/C
6
I
X1, X2
7, 8
I
EFI
5
I
PCLK
13
O
ARDYEN
17
I
ARDY
1
I
SRDYEN
3
I
SRDY
2
I
READY
4
O
S0, S1
15,16
I
RESET
12
O
RES
11
I
VCC GND
18
9
2
82C284 Functional Description
Introduction The 82C284 generates the clock, ready, and reset signals required for 80C286 processors and support components. The 82C284 is packaged in an 18-pin DIP and contains a crystal controlled oscillator, clock generator, peripheral clock generator, MULTIBUS(R) ready synchronization logic, and system reset generation logic. Clock Generator The CLK output provides the basic timing control for an 80C286 system. CLK has output characteristics sufficient to drive CMOS devices. CLK is generated by either an internal crystal oscillator, or an external source as selected by the F/C input pin. When F/C is LOW, the crystal oscillator drives the CLK output. When F/C is HIGH, the EFI input drives the CLK output. The F/C pin on the Intersil 82C284 is dynamically switchable. This allows the CLK frequency to the processor to be changed from one frequency to another in a running system. With this feature, a system can be designed which operates at maximum speed when needed, and then dynamically switched to a lower frequency to implement a low-power mode. The lower frequency can be anything down to, but excluding, DC. The following 3 conditions apply when dynamically switching the F/C pin (see Figure 1): 1) The CLK is stretched in the low portion of the 2 phase of its cycle during transition from one CLK frequency to the other (see Waveforms). 2) When switching CLK frequency sources, there is a maximum transition latency of 2.5 clock cycles of the frequency being switched to, from the time CLK freezes low, until CLK restarts at the new frequency (see Waveforms). The maximum latency from the time F/C is dynamically switched, to the time CLK freezes low, is 4 CLK cycles (see Waveforms).
3)
The following steps describe the sequence of events that transpire when F/C is dynamically switched: A) F/C switched from high (using EFI input) to low (using the crystal input X1 - see Figure 1A). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the crystal frequency on the rising edge of Xl, after the second falling edge of X1. B) F/C switched from low (using the crystal input Xl) to high (using the EFI input - see Figure 1B). 1) The state of F/C is sampled when both CLK and PCLK are high until a change is detected. 2) On the second following falling edge of PCLK, CLK is frozen low. 3) CLK restarts at the EFI input frequency on the falling edge of EFl after the second rising edge of EFI.
1 1 CLK
2
1
2
1
2
PCLK
2
F/C
X1 3
FIGURE 1A. F/C SWITCHED FROM HIGH (USING EFI INPUT) TO LOW (USING THE CRYSTAL INPUT X1)
3
82C284
1
CLK
1 2 1 2 2 1 2
PCLK
F/C
EFI
3
FIGURE 1B. F/C SWITCHED FROM LOW (USING THE CRYSTAL INPUT X1) TO HIGH (USING THE EFI INPUT) FIGURE 1. DYNAMICALLY SWITCHING THE F/C PIN
The 82C284 provides a second clock output, PCLK, for peripheral devices. PCLK is CLK divided by two. PCLK has a duty cycle of 50% and CMOS output drive characteristics. PCLK is normally synchronized to the internal processor clock. After reset, the PCLK signal may be out of phase with the internal processor clock. The S1 and S0 signals of the first bus cycle are used to synchronize PCLK to the internal processor clock. The phase of the PCLK output changes by extending its HIGH time beyond one system clock (see waveforms). PCLK is forced HIGH whenever either S0 or S1 were active (LOW) for the two previous CLK cycles. PCLK continues to oscillate when both S0 and S1 are HIGH. Since the phase of the internal processor clock will not change except during reset, the phase of PCLK will not change except during the first bus cycle after reset. Oscillator The oscillator circuit of the 82C284 is a linear Pierce oscillator which requires an external parallel resonant, fundamental mode, crystal. The output of the oscillator is internally buffered. The crystal frequency chosen should be twice the required internal processor clock frequency. The crystal should have a typical load capacitance of 32pF. X1 and X2 are the oscillator crystal connections. For stable operation of the oscillator, two loading capacitors are recommended, as shown in Table 1. The sum of the board capacitance and loading capacitance should equal the values shown. It is advisable to limit stray board capacitances (not including the effect of the loading capacitors or crystal capacitance) to less than 10pF between the X1 and X2 pins. Decouple VCC and GND as close to the 82C284 as possible with a 0.1F polycarbonate capacitor.
TABLE 1. 82C284 CRYSTAL LOADING CAPACITANCE VALUES Cl CAPACITANCE (PIN 7) 60pF 25pF 15pF C2 CAPACITANCE (PIN 8) 40pF 15pF 15pF
CLK Termination Due to the CLK output having a very fast rise and fall time, it is recommended to properly terminate the CLK line at frequencies above 10MHz to avoid signal reflections and ringing. Termination is accomplished by inserting a small resistor (typically 10-74) in series with the output, as shown in Figure 2. This is known as series termination. The resistor value plus the circuit output impedance (approximately 25) should be made equal to the impedance of the transmission line.
CLK OUT
R Z
CLOSELY PLACED LOADS
RO 25
TRANSMISSION LINE Z CLOSELY PLACED LOADS
FIGURE 2. SERIES TERMINATION
Reset Operation The reset logic provides the RESET output to force the system into a known, initial state. When the RES input is active (LOW), the RESET output becomes active (HIGH), RES is synchronized internally at the falling edge of CLK before generating the RESET output (see waveforms). Synchronization of the RES input introduces a one or two CLK delay before affecting the RESET Output. At power up, a system does not have a stable VCC and CLK. To prevent spurious activity, RES should be asserted until VCC and CLK stabilize at their operating values. 80C286 processors and support components also require their RESET inputs be HIGH a minimum of 16 CLK cycles. An RC network, as shown in Figure 3, will keep RES LOW long enough to satisfy both needs. A Schmitt trigger input with hysteresis on RES assures a single transition of RESET with an RC circuit on RES. The hysteresis separates the input voltage level at which the circuit output switches from HIGH to LOW from the input voltage level at which the circuit output switches from LOW to HIGH. The RES HIGH to LOW input transition voltage is lower than the RES
CRYSTAL FREQUENCY 1MHz to 8MHz 8MHz to 20MHz 20MHz to 25MHz
4
82C284
LOW to HIGH input transition voltage. As long as the slope of the RES input voltage remains in the same direction (increasing or decreasing) around the RES input transition voltage, the RESET output will make a single transition.
VCC C1 82C284 11 47 + 10F RES 6 F/C 7 X1 8 X2 82C284 4 READY VCC 1N914 18 READY VCC DECOUPLING CAPACITOR 10k CLK VCC 10 CLK 80C286 CPU OR SUPPORT COMPONENT
FIGURE 4. RECOMMENDED CRYSTAL AND READY CONDITIONS FIGURE 3. TYPICAL RC RES TIMING CIRCUIT
Ready Operation The 82C284 accepts two ready sources for the system ready signal which terminates the current bus cycle. Either a synchronous (SRDY) or asynchronous ready (ARDY) source may be used. Each ready input has an enable (SRDYEN and ARDYEN) for selecting the type of ready source required to terminate the current bus cycle. An address decoder would normally select one of the enable inputs. READY is enabled (LOW), if either SRDY + SRDYEN = 0 or ARDY + ARDYEN = 0 when sampled by the 82C284 READY generation logic. READY will remain active for at least two CLK cycles. The READY output has an open-drain driver allowing other ready circuits to be wired with it, as shown in Figure 4. The READY signal of an 80C286 system requires an external pull-up resistor. To force the READY signal inactive (HIGH) at the start of a bus cycle, the READY output floats when either S1 or S0 are sampled LOW at the falling edge of CLK. Two system clock periods are allowed for the pull-up resistor to pull the READY signal to VlH . When RESET is active, READY is forced active one CLK later (see Waveforms).
Figure 5 illustrates the operation of SRDY and SRDYEN. These inputs are sampled on the falling edge of CLK when S1 and S0 are inactive and PCLK is HIGH. READY is forced active when both SRDY and SRDYEN are sampled as LOW. Figure 6 shows the operation of ARDY and ARDYEN These inputs are sampled by an internal synchronizer at each falling edge of CLK. The output of the synchronizer is then sampled when PCLK is HIGH. If the synchronizer resolved both the ARDY and ARDYEN as active, the SRDY and SRDYEN inputs are ignored. Either ARDY or ARDYEN must be HIGH at the end of T S, therefore, at least one wait state is required when using the ARDY and ARDYEN inputs as a basis for generating READY. READY remains active until either S1 or S0 are sampled LOW, or the ready inputs are sampled as inactive.
5
82C284
TS CLK
TC
TC
T1
PCLK
S1 * S0 VIH ARDYEN SRDYEN + SRDY
READY
FIGURE 5. SYNCHRONOUS READY OPERATION
TS TC TC T1
CLK
PCLK
S1 * S0 VIH SRDYEN ARDY + ARDYEN
READY
FIGURE 6. ASYNCHRONOUS READY OPERATION
6
82C284
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied. . . . . GND -0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Thermal Information
Thermal Resistance
JA (oC/W) JC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 80 20 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Gates Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . +300oC ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Operating Conditions
Operating Temperature Range C82C284. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC I82C284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V EFI Rise Time (from 0.8V to 3.2V) . . . . . . . . . . . . . . . . . . 8ns (Max) EFI Fall Time (from 3.2 to 0.8V) . . . . . . . . . . . . . . . . . . . . 8ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
TA = 0oC to +70oC (CD82C284); VCC = 5V 10% TA = -40oC to +85oC (ID82C284)
SYMBOL V IL VIH VIHC VIHR VHYS VOL V OH VOLR VOLC VOHC IIL ICCOP
PARAMETER Input LOW Voltage Input HIGH Voltage EFI, F/C Input HIGH Voltage RES HIGH Voltage RES Input Hysteresis RESET, PCLK Output LOW Voltage RESET, PCLK Output HIGH Voltage READY Output LOW Voltage CLK Output LOW Voltage CLK Output HIGH Voltage Input Leakage Current Active Power Supply Current
MIN 2.2 3.2 VCC-0.8 0.5 VCC-0.4 VCC-0.4 -10 -
MAX 0.8 0.4 0.4 0.4 10 60 48
UNITS V V V V V V V V V V A mA mA VCC = 4.5V VCC = 5.5V VCC = 5.5V VCC = 5.5V VCC = 5.5V
TEST CONDITIONS
IOL = 5mA, VCC = 4.5V, Note 2 IOH = -1mA, VCC = 4.5V, Note 2 IOL = 10mA, VCC = 4.5V, Note 2 IOL = 5mA, VCC = 4.5V, Note 2 IOH = -5mA, VCC = 4.5V, Note 2 VIN = VCC or GND, VCC = 5.5V 82C284-12 (Note 1) 82C284-10 (Note 1)
NOTES: 1. ICCOP measured at 10MHz for 82C284-10 and at 12.5MHz for the 82C284-12. V IN = GND or VCC, VCC = 5.5V outputs unloaded. 2. Interchanging of force and sense conditions is permitted.
AC Electrical Specifications
TA = 0oC to +70oC (CD82C284); VCC = 5V 10% TA = -40oC to +85oC (lD82C284) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Waveforms, Unless Otherwise Noted. 10MHz 12.5MHz MIN 16 20 18 16 MAX UNIT ns ns ns ns TEST CONDITIONS At VCC/2 (Note 8) At VCC/2 (Note 8)
SYMBOL t1 t2 5A 5B
PARAMETER EFl LOW Time EFI HIGH Time Status Setup Time for Status Going Active Status Setup Time for Status Going Inactive
MIN 20 20 20 20
MAX -
7
82C284
AC Electrical Specifications
TA = 0oC to +70oC (CD82C284); VCC = 5V 10% (Continued) TA = -40oC to +85oC (lD82C284) AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Waveforms, Unless Otherwise Noted. 10MHz SYMBOL t6 t7 t8 t9 t10 t11 t12 t13 t14 t16 t17 t18 t21 t22 t23 t24 t25 t26 NOTES: 1. VCC = 4.5V and 5.5V unless otherwise specified. CLK loading: C L = 100pF. 2. With the internal crystal oscillator using recommended crystal and capacitive loading; or with the EFI input meeting specifications t1 and t2. The recommended crystal loading for CLK frequencies of 8MHz to 20MHz are 25pF from pin X1 to ground, and 15pF from pin X2 to ground; for CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND. These recommended values are +5pF and include all stray capacitance. Decouple V CC and GND as close to the 82C284 as possible. 3. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge. 4. The pull-up resistor value for the READY pin is 620 with the rated 150pF load. 5. t16 refers to any allowable CLK period. 6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 requirements. 7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES waveform for RES active and to 4.2V on the RES waveform for RES inactive. 8. Input test waveform characteristics: VIL = 0V, VlH = 4.5V. UNTESTED SPECIFICATIONS 10MHz SYMBOL CIN t15A t15B PARAMETER Input Capacitance MIN MAX 10 12.5MHz MIN MAX 10 UNITS pF CONDlTIONS (NOTE 1) FREQ = 1MHz, All measurements are referenced to device GND, TA = +25oC (Note 2) (Note 3) PARAMETER Status Hold Time F/C Setup Time F/C Hold Time SRDY or SRDYEN Setup Time SRDY or SRDYEN Hold Time ARDY or ARDYEN Setup Time ARDY or ARDYEN Hold Time RES Setup Time RES Hold Time CLK Period CLK LOW Time CLK HIGH Time READY Inactive Delay READY Active Delay PCLK Delay RESET Delay PCLK LOW Time PCLK HIGH Time MIN 1 15 15 15 2 5 30 20 10 50 12 16 5 t16 -10 t16 -10 MAX 24 20 27 12.5MHz MIN 1 15 15 15 2 5 25 18 8 40 11 13 5 t16 -10 t16 -10 MAX 18 16 26 ns ns ns ns ns ns na ns (Notes 2, 6) (Notes 2, 6) At 0.8V (Note 4), Test Condition 2 At 0.8V (Note 4) CL = 75pF, Test Condition 1 CL = 75pF, Test Condition 3 CL = 75pF (Note 5) CL= 75pF (Note 5) ns ns ns ns ns ns (Note 3) (Note 3) (Notes 3, 7) (Notes 3, 7) UNIT ns TEST CONDITIONS
EFI HIGH to CLK LOW Delay EFI LOW to CLK HIGH Delay
-
30 35
-
25 30
ns ns
8
82C284
UNTESTED SPECIFICATIONS (Continued) 10MHz SYMBOL t19 t20 t27 NOTES: 1. The parameters listed in this table are controlled via design or, process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 2. Measured from 3.2V on the EFI waveform to 1.0V on the CLK. 3. Measured from 0.8V on the EFI waveform to 3.6V on the CLK. 4. Measured from 3.6V on the X1 input to 3.6V on the CLK. PARAMETER CLK Rise Time CLK Fall Time X1 HIGH to CLK MIN MAX 8 8 35 12.5MHz MIN MAX 8 8 30 UNITS ns ns ns CONDlTIONS (NOTE 1) 1.0V to 3.6V, CL = 100pF 3.6V to 1.0V, CL = 100pF (Note 4)
AC Specifications
EFI INPUT 3.2V 0.8V tDELAY (MAX) VCC - 0.4V CLK OUTPUT tSETUP tHOLD F/C INPUT 3.2V 3.2V 0.8V 0.8V 3.8V 0.4V 3.6V 1.0V 3.6V 1.0V 0.4V 3.8V 0.4V
AC Test Condition
VCC
RL DEVICE OUTPUT CL
FIGURE 8.
RES INPUT
VCC - 0.8V 0.8V 0.8V
VCC - 0.4V 0.4V
TEST CONDITION 1 2 3
RL 750 620
CL 75pF 150pF 75pF
2.4 OTHER DEVICE INPUT 2.0V 2.0V 0.8V 0.8V 0.4V tDELAY (MAX) tDELAY (MIN) DEVICE OUTPUT 2.0V 0.8V
FIGURE 7. A.C. DRIVE, SETUP, HOLD AND DELAY TIME MEASUREMENT POINTS
9
82C284 Waveforms
t1 EFI t19 CLK t17 t20 t15B t18 t2 t16
t15A
NOTE: 1. The EFI input LOW and HIGH times as shown are required to guarantee the CLK LOW and HIGH times shown. FIGURE 9. CLK AS A FUNCTION OF EFI
t16 CLK t14 t13 RES t24 RESET DEPENDS ON STATE OF PREVIOUS RES READY t22 t21 t24 SEE NOTE t13 t14
NOTE: 1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown. FIGURE 10. RESET AND READY TIMING AS A FUNCTION OF RES WITH S1, S0, ARDY + ARDYEN, AND SRDY + SRDYEN HIGH
1 CLK t6 S1 * S0 t5A PCLK
TS
2
1
TC
2
t5B t6 t23 t25 UNDEFINED IF THIS IS FIRST BUS CYCLE t9 t10 NOTE 1 t11 t12 t11 t12 t23 t26
SRDY + SRDYEN
ARDY + ARDYEN t21 READY NOTE 2 t21 t22
NOTES: 1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown. 2. If SRDY + SRDYEN or ARDYEN are active before and/or during the first bus cycle after RESET, READY may not be deasserted until the falling edge of 2 of TS. FIGURE 11. READY AND PCLK TIMING WITH RES HIGH
10
82C284 Waveforms
(Continued)
1 CLK PCLK t7 F/C X1 t8 t27 2 1 2 1 2
CLK 1 PCLK t7 t8 EFI t15B 2 1 2 1 2
F/C
NOTE: 1. This is an asynchronous input. The setup and hold times are required to guarantee the response shown. FIGURE 12. CLK AS A FUNCTION OF F/C, PCLK, X1, AND EFI DURING DYNAMIC FREQUENCY SWITCHING
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